Network On Chip

As VLSI technology becomes smaller, and the number of modules on a chip increases, on-chip communication solutions are evolving in order to support the new inter-module communication demands. Traditional solutions, which were based on a combination of shared-buses and dedicated module to- module wires, have hit their scalability limit, and are no longer adequate for sub-micron technologies. Current chip designs incorporate more complex multilayered and segmented interconnection buses.

More recently, chip architects have begun employing on-chip network-like solutions. This evolution of on-chip interconnects may evoke feelings of déjà vu among networking old-timers. We believe that the considerations that have driven data communication from shared buses to packet-switching networks (spatial reuse, multi-hop routing, flow and congestion control, and standard interfaces for design reuse, etc.) will inevitably drive VLSI designers to use these principles in on-chip interconnects. In other words, we expect the future chip design to incorporate a full fledged network-on-a-chip (NoC), consisting of a collection of links and routers and a new set of protocols that govern their operation. Although papers and companies have started to addressed on-chip network architectures, the field is still in its infancy, and many challenges have yet to be tackled.
 
In designing a NoC, one has to address all the classical networking issues. Addressing and routing schemes need to be devised in order to allow packets traversing the same links to be routed to diverse destinations. Names meaningful to applications (such as memory and I/O addresses) need to be translated into routing efficient labels. Since the timely delivery of certain types of traffic (or signals) on the chip is crucial for performance, support for multiple quality-of service (QoS) requirements are also essential. Similarly, a NoC should support network level congestion control in order to accommodate excessive traffic conditions. Where congestion control is employed, fairness issues need to be considered as well.
 
Since problems of this type have been extensively studied in the networking realm, as well as for off-chip interconnection networks, one may be tempted to employ well developed networking/interconnection solutions in the NoC context. Nevertheless, a direct adaptation of network protocols to NoCs is impossible, due to the different communication requirements, cost considerations, and architectural constraints. The primarily considerations in VLSI are minimizing power dissipation and area. This has a number of implications on NoC design. First, NoC components should be extremely simple, so as to allow implementing them with a small number of logic gates and to expend as little energy as possible. In addition, power considerations render shortest-path routes highly desirable, while area considerations dictate the use of small routing tables.
 
Beyond the distinctive cost considerations, the requirements from a NoC also differ from their off-chip counterparts. For example, on-chip network topologies are quite restricted– they are laid onto planar layers (in silicon and/or metal), and are therefore often organized as (possibly partial) grids. Thus, elaborate layouts like high-dimension hypercubes and butterflies, which are often employed in interconnection networks, are not cost-effective for NoCs.
 
Moreover, NoC topologies are fixed throughout their lifetimes. That is, they do not need to support the dynamic addition or removal of network-attached modules. Furthermore, the NoC is synthesized anew for each design eliminating the need for standard network protocols; i.e., there is no advantage in backward compatibility of NoC protocols and architectures employed in a new chip designs with those used in previous designs, beyond the use of standard network interfaces to allow the reuse of modules, across design generations. This means that the future chip designer will be able to select the best NoC architecture among a plurality of architectures offered by the chip synthesis tools, customized to his specific requirements. Another crucial aspect of on-chip network design is meeting strict QoS requirements for distinct types of in-chip traffic, such as interrupt signals or fetching instructions and data from caches to processors.
 
Finally, the NoC design process dramatically differs from that of classical networks, allowing a new important dimension of freedom— the ability to alter the physical layout of the network routers and links along with the chip module placements. This enables the designer to optimize the NoC geography and resource allocation according to traffic and layout constraints. Moreover, if traffic requirements are known ahead of time (as is typical for many special purpose SoCs), the NoC’s topological layout and capacity allocation can be optimized to this traffic with any desired routing protocol; this eliminates the need for a high cost load-balanced routing protocol. Another new dimension in NoC design is the fact the in-chip distances are very small and communication links do not necessarily dominate the hardware costs. Consequently, centralized NoC control or the provision of multiple off-band channels may be a viable design choice.
 
The aforementioned differences between the on-chip environment and classical network settings imply that NoC design requires the development of new solutions. Hence, NoC is a promising research field, which can have a large practical impact on the future of VLSI, and where networking expertise will be valuable. The NoC area presents a fertile ground where frustrated network architects may harness their abilities to design not one, but many diverse network architectures! In order to advance this field, there is a need for crisp definitions of models, requirements, costs, and problems. Since different chips may require different NoCs, a classification of NoC models and problems that arise in each category is also of essence.
 
A tutorial describing these challenges and our NoC group work was presented in NOCS 2009 at San Diego. Our slides can be viewed here: part 1, part 2 and part3. Our NoC group activity is part of the Technion Matrics project.